1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method of fabricating a stacked capacitor of a dynamic random access memory (DRAM).
2. Description of the Related Art
DRAM is a kind of widely used ICs. The data in a DRAM are saved by charging or discharging. Therefore, the charge saved in the capacitor of the DRAM must be in an operation range to make sure of that the data can be correctly read and written. Because of the trend of higher integrity ICs, the size of the DRAM is gradually reduced and simultaneously, the size of the capacitor is cut down. However, for a storage capacitor of a fixed operation voltage, as the distance of the electrodes and the dielectric constant of the dielectric layer are fixed, the amount of saved charge then depends on the area of capacitor plate. The charge saved in a capacitor is undesirably reduced as the area occupied by the DRAM capacitor is shrunk.
FIG. 1A to FIG. 1D shows a method of fabricating a capacitor of a DRAM. As shown in FIG. 1A, a silicon substrate 10 is firstly provided, wherein a metal-oxide-semiconductor (MOS) 11 and a field oxide 12 are already formed. The MOS 11 and the field oxide 12 are covered by an insulating layer 15 and a contact window 20 is formed on a source/drain region 16 of the MOS device 11.
Next, a first polysilicon layer 21 is deposited over the substrate 10. The first polysilicon layer 21 is then doped and annealed to increase its conductivity. Next, the first polysilicon layer 21 is patterned to form a lower electrode of a capacitor, as shown in FIG. 1B. A dielectric layer 26 is then deposited over the lower electrode of the capacitor, the first polysilicon layer 21, as shown in FIG. 1C. A second polysilicon layer 28 having a thickness of about 1000 .ANG. to 2000 .ANG. is deposited on the surface of the dielectric layer 26 and then doped by, for example, POCl.sub.3, to increase its conductivity. Therefore, the upper electrode 28 of the capacitor is formed and the capacitor structure is completed, as shown in FIG. 1D.
With the requirement of high integrity device, the capacitor fabricated by the above-mentioned process fails in being correctly read and written.
Consequently, it is an object of the invention to provide a method of fabricating a stacked capacitor of a DRAM, which uses a number of doped polysilicon and tungsten silicide layers to form the lower electrode of the capacitor. The doped polysilicon layers and the tungsten suicide layers are selectively etched to form a number of lateral trenches at the sidewall of the stacked structure to increase the surface area of the electrode and also the capacitance. By this way, the capacitance of the lateral trench stacked capacitor can be risen to about 1.5 times of the conventional capacitor without the complicate process steps as forming the conventional stacked capacitor. Moreover, the amount of capacitance can be controlled by the number of the polysilicon layers and the tungsten silicide layers.